pi6c20800b features ? ? pin-to-pin compatible to ics85352i ? ? fmax 500 mhz ? ? propagation delay < 4ns ? ? output-to-output skew < 100ps ? ? 12 pairs of diferential lvpecl outputs ? ? selectable diferential clk and /clk inputs ? ? clk, /clk pair accepts lvds, lvpecl, lvhstl, sstl and hcsl input level ? ? select input accept cmos/lvttl levels ? ? 2.5v/3.3v power supply ? ? operating temperature: -40c to +85c ? ? packaging (pb-free & green): ?? 48-pin tqfp (fa) pi6c485352 1 pi6c485352 rev. a 01/24/13 pin confguration (48-pin tqfp) description te pi6c485352 is a high-performance low-skew lvpecl fanout bufer. pi6c485352 features two selectable diferential inputs and translates to twelve lvpecl output pairs. te inputs can also be confgured to single-ended with external resistor bias circuit. te clk input accepts lvpecl, lvds, lvhstl, sstl or hcsl signals. te pi6c485352 is ideal for diferential to lvpecl translations and/or lvpecl clock distribution. typical clock translation and distribution applications are data- communications and telecommunications. applications ? ? networking systems including switches and routers ? ? high frequency backplane based computing and telecom platforms 2.5v/3.3v, 500 mhz twelve 2-to-1 differential lvpecl clock multiplexer 1 2 3 /q1 4 q2 5 q1 6 q3 7 /q9 8 /q2 q6 q7 /q7 /q8 /q3 2019181716151413 q0 /q0 q10 9q4 12 10/q4 11 21 22 23 24 36 35 34 33 32 31 30 29 28 25 27 26 4142434445464748 40 39 38 37 q5 /q5 /q6 q8 q9 /q10 /q11 q11 v cdd /clk0 sel2 clk0 sel1 sel0 sel6 sel7 sel8 /clk1 clk1 v cco v cco v ee sel5 v cc sel4 sel3 sel9 sel10 sel11 v cc v ee v cco sel [0:11] clk0 /clk0 clk1 /clk1 1 0 0 1 q0 /q0 q11 /q11 12 block diagram 13-0003
2 pi6c485352 rev. a 01/24/13 pin # pin name ty pe description 1, 2 3, 4 5, 6 7, 8 9, 10 11, 12 25, 26 27, 28 29, 30 31, 32 33, 34 35, 36 q0, /q0 q1, /q1 q2, /q2 q3, /q3 q4, /q4 q5, /q5 /q11, q11 /q10, q10 /q9,q9 /q8,q8 /q7,q7 /q6,q6 output diferential lvpecl output pairs. lvpecl inter - face levels 13, 24 37, 4 8 v cco power output supply pins 14, 23 v ee ground pins 15, 22 v cc core supply pins 16, 17 18, 19 20, 21 40, 41 42, 43 44, 45 sel5, sel4, sel3, sel9, sel10, sel11, sel8, sel7, sel6, sel0, sel1, sel2 pulldown clock select inputs. lvcmos/lvttl interface levels 38 clk1 pulldown non-inverting diferential clock input 39 /clk1 pullup/pulldown inverting diferential clock input 46 clk0 pulldown non-inverting diferential clock input 47 /clk0 pullup/pulldown inverting diferential clock input pinout table pi6c485352 2.5v/3.3v, 500 mhz twelve 2-to-1 diferential lvpecl clock multiplexer 13-0003
3 pi6c485352 rev. a 01/24/13 pin characteristics symbol parameter test condition min. ty p. max. units cin input capacitance p pullup input pullup esistance k pulldon input pulldon esistance k maximum ratings (above which the useful life may be impaired. for user guidelines, not tested) note: stresses greater tan tose listed under mximum tins may cause permanent damage to te deice. is is a stress rating only and unctional operation o te deice at tese or any oter conditions aboe tose indicated in te operational sections o tis specication is not implied. exposure to absolute maximum rating conditions or extended periods may aect reliability. symbol parameter test condition min. ty p. max. units cc cco supply oltage eerenced to nd . in input oltage eerenced to nd . cc . outputs i o surge current m tst storage temperature c package termal impedence c control input function table selx selected clock inputs cl cl cl cl pi6c485352 2.5v/3.3v, 500 mhz twelve 2-to-1 diferential lvpecl clock multiplexer 13-0003
4 pi6c485352 rev. a 01/24/13 differential dc characteristics (ta = -40 c to +85 c , vcc = 3.3v 10%, vcco = 2.5v 5% to 3.3v 10%) pete eto coto . t . . t i ih input high current clk0, clk1 v in = v cc = 3.6v 150 a /clk0, /clk1 v in = v cc = 3.6v 150 a i il input low current clk0, clk1 v cc = 3.6v, v in = 0v -5 a /clk0, /clk1 v cc = 3.6v, v in = 0v -150 a v pp peak-to-peak voltage 0.15 1.3 v v cmr common mode input voltage (1) v ee +0.5 v cc -0.85v v v oh output high voltage (2) v cco = 3.3v or 2.5v v cco -1.4 v cco -0.9 v v ol output low voltage (2) v cco = 3.3v or 2.5v v cco -2.0 v cco -1.7 v note: 1. outputs terminated with 50 to v cco -2.0v lvcmos/lvttl dc characteristics (ta = -40 c to +85 c , vcc = 3.3v 10%, vcco = 2.5v 5% to 3.3v 10%) o pete coto . t . . t v ih input high voltage sel0:sel11 2 v cc +0.3 v v il input low voltage sel0:sel11 -0.3 0.8 i ih input high current sel0:sel11 vin = vcc = 3.6v 150 a i il input low current sel0:sel11 vin = 0v, vcc = 3.6v -5 a symbol parameter test condition min. ty p. max. units v cc power supply voltage 3.0 3.3 3.6 v v cco output power supply voltage 2.375 3.6 v t a ambient temperature -40 85 c i ee power supply current 200 ma operating conditions pi6c485352 2.5v/3.3v, 500 mhz twelve 2-to-1 diferential lvpecl clock multiplexer 13-0003
5 pi6c485352 rev. a 01/24/13 ac characteristics (ta = -40 c to +85 c , vcc = 3.3v 10%, vcco = 2.5v 5% to 3.3v 10%) pete eto coto . t . . t fmax output frequency 500 mhz tpd propagation delay (1) 4 ns tsk output-to-output skew (2) 100 ps tskpp part-to-part skew (3) 500 ps tr/tf output rise/fall time 20% - 80% 150 700 ps odc output duty cycle 45 55 % t j bufer additive jitter rms 0.05 ps note: 1. measured from the diferential input to the diferential output crossing point 2 defned as skew between outputs at the same supply voltage and with equal loads. measured at the output diferential crossing point. 3. defned as skew between outputs on diferent parts operating at the same supply voltage and with equal loads. measured at the outputs diferential crossing point. pi6c485352 2.5v/3.3v, 500 mhz twelve 2-to-1 diferential lvpecl clock multiplexer 13-0003
6 pi6c485352 rev. a 01/24/13 v 1k c1 single ended clock input cc clk1 r2 r1 1k nclk1 v_ref 0.1f applications information wiring the diferential input to accept single ended levels igure shos ho the dierential input can e ired to accept singleended levels e reerence voltage is gener ated the ias resistors and is ias circuit should e placed as close as possile to the input pin e ratio o and should e adusted to postion the at the center o the input voltage sing or eaple i the input cloc sing is and should e and figure 1: single-ended signal driving differential input pi6c485352 2.5v/3.3v, 500 mhz twelve 2-to-1 diferential lvpecl clock multiplexer 13-0003
7 pi6c485352 rev. a 01/24/13 ordering information ordering number package code package description pice pbree reen pin mil ide tp ? termal characteristics can be found on the company web site at www.pericom.com/packaging/ ? e = pb-free and green ? x sufx = tape/reel packaging mechanical: 48-pin tqfp (fa) 1 description: 48-pin thin quad flat package (tqfp) package code: fa48 document control #: pd-2056 revision: - - notes: 1) all dimensions are in millimeters, angles in degrees 2) ref jedec: mo-026d, variation abc 3) dimensions do not include mold protrusion date: 02/16/06 06-0182 pi6c485352 2.5v/3.3v, 500 mhz twelve 2-to-1 diferential lvpecl clock multiplexer 13-0003
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